ASIC / SOC Verification Engineer

This job is no longer active. View similar jobs.

POST DATE 9/8/2016
END DATE 10/8/2016

Confidential Company Santa Clara, CA

Santa Clara, CA
AJE Ref #
Job Classification
Full Time
Job Type
Company Ref #
Mid-Career (2 - 15 years)


In this role, the selected candidate must have a strong background in SOC verification using UVM, System Verilog. Job Responsibilities:Strong background in SOC verification using UVM, System verilogExpert in C/C++ and Scripting using PerlMinimum 5 years of experienceExperienced working on Video and Image processing is plusPreferred Experience : 5+Sound knowledge in Verilog / System verilog.Experience with verification methodology such UVM/VMM/OVM. UVM is preferred.UVM Testbench, coding and good understanding of design issues in RTL.Prior hands on experience on integration and debug of Full chipEnvironment is preferred.Experience in scripting .Skill set / expertise: UVM and low power verification, testbench development.Number of open positions : 10Location : Santa Clara