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Design Verification Engineer

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POST DATE 8/27/2016
END DATE 11/9/2016

Maxim Integrated Dallas, TX

Company
Maxim Integrated
Job Classification
Full Time
Company Ref #
2028BR
AJE Ref #
575990411
Location
Dallas, TX
Experience
Mid-Career (2 - 15 years)
Job Type
Regular
Education
Masters Degree

JOB DESCRIPTION

APPLY
Minimum Degree Required
Master's Degree

Career Level
Non-Manager - Experienced (5+ years exp)

Job Description

Maxim Integrated is seeking exceptional Verification engineers to help drive Verification of complex Mixed-Signal SoCs using state-of-the-art Advanced Verification Techniques. This engineer will work in a team-oriented environment to deliver advanced verification components. As a key member of the team, he/she will be responsible for:

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Understanding the expected design functionality
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Work independently
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Developing verification-plans
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Implement verification infrastructure based on cutting edge methodologies and tools.
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UVM based Verification component development for Mixed-Signal designs
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Coverage closure using advanced analysis
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Methodology support
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Operation and maintenance
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Pre-and post-silicon verification & debug to achieve verification goals.

Must be a good team player and have the ability to handle all verification implementation tasks independently in a multi-disciplinary team environment. Must have a good understanding of advanced verification methodologies Metrics & Plan Driven Verification and have hands-on experience with: UVM/OVM/eRM.

Minimum Qualifications

Must have:

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MSEE or MSCE with 5+ years of directly related industry experience in ASIC/SoC Verification
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Expert level knowledge of testbench development using Object Oriented System Verilog
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Hands on experience and expert-level knowledge of advanced verification methodologies (OVM/UVM with System Verilog)
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Expert level knowledge of Coverage Driven Verification Coverage Model design & implementation using HVLs
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Verification Planning
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Assertion based checks (PSL/SVA)
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Team-player: ability to forge and maintain relationships with peer-organizations
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Simulation & debug
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Gate-level bring up * Scripting: Perl/Ruby/Tcl

* Good communications skills

Maxim Integrated is an EEO/AA/Disability/Vets Employer

Preferred Qualifications

Plus:

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Experience with Mixed Signal verification
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Experience with Assertions & Coverage for Analog/Mixed-Signal
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Modeling of analog (Real Number Models)
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Formal Verification
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Experience with Cadence based Verification tools: IUS, ePlanner, eManager, IFV, Conformal
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TLM, Virtual prototype
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Experience working with off-shore flex resources

We are hiring only the best! This is a key opportunity in a growing team and company.


Percentage of Travel
0% - 10%

Relocation Assistance Available
Yes

Visa Sponsorship Available
Yes