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Design Verification Engineer

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POST DATE 8/27/2016
END DATE 11/9/2016

Maxim Integrated Dallas, TX

Dallas, TX
AJE Ref #
Job Classification
Full Time
Job Type
Company Ref #
Mid-Career (2 - 15 years)
Masters Degree


Minimum Degree Required
Master's Degree

Career Level
Non-Manager - Experienced (5+ years exp)

Job Description

Maxim Integrated is seeking exceptional Verification engineers to help drive Verification of complex Mixed-Signal SoCs using state-of-the-art Advanced Verification Techniques. This engineer will work in a team-oriented environment to deliver advanced verification components. As a key member of the team, he/she will be responsible for:


Understanding the expected design functionality

Work independently

Developing verification-plans

Implement verification infrastructure based on cutting edge methodologies and tools.

UVM based Verification component development for Mixed-Signal designs

Coverage closure using advanced analysis

Methodology support

Operation and maintenance

Pre-and post-silicon verification & debug to achieve verification goals.

Must be a good team player and have the ability to handle all verification implementation tasks independently in a multi-disciplinary team environment. Must have a good understanding of advanced verification methodologies Metrics & Plan Driven Verification and have hands-on experience with: UVM/OVM/eRM.

Minimum Qualifications

Must have:


MSEE or MSCE with 5+ years of directly related industry experience in ASIC/SoC Verification

Expert level knowledge of testbench development using Object Oriented System Verilog

Hands on experience and expert-level knowledge of advanced verification methodologies (OVM/UVM with System Verilog)

Expert level knowledge of Coverage Driven Verification Coverage Model design & implementation using HVLs

Verification Planning

Assertion based checks (PSL/SVA)

Team-player: ability to forge and maintain relationships with peer-organizations

Simulation & debug

Gate-level bring up * Scripting: Perl/Ruby/Tcl

* Good communications skills

Maxim Integrated is an EEO/AA/Disability/Vets Employer

Preferred Qualifications



Experience with Mixed Signal verification

Experience with Assertions & Coverage for Analog/Mixed-Signal

Modeling of analog (Real Number Models)

Formal Verification

Experience with Cadence based Verification tools: IUS, ePlanner, eManager, IFV, Conformal

TLM, Virtual prototype

Experience working with off-shore flex resources

We are hiring only the best! This is a key opportunity in a growing team and company.

Percentage of Travel
0% - 10%

Relocation Assistance Available

Visa Sponsorship Available