Front End IC Design Engineer
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* Develop micro-architecture specification for Memory, Cache, I/O, Acceleration or Network Subsystems
* Implement the RTL code for the unit
* Collaborate with verification team in the development of Testplan, Testbench and Tests; and assist in debugging of test failures in simulation and emulation environments
* Support physical design team in writing timing constraints, analyze timing violations and perform timing fixes in RTL.
* Own and drive future design of additional system blocks
* Total engineering minimum experience required is typically a BS degree and 9 years of experience, an MS degree and 6 years of experience or a PhD and x years of experience
* MSEE or MSCS preferred.
* Must have working knowledge of Verilog, pipelining, various flow control methods
IF YOU ARE LOCATED OUTSIDE USA, PLEASE BE SURE TO FILL OUT A HOME ADDRESS AS THIS WILL BE USED FOR FUTURE CORRESPONDENCE.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability or protected veteran status.