IC Design Verification Engineer
This job is no longer active.
View similar jobs.
POST DATE 8/25/2016
END DATE 10/14/2016
Santa Clara, CA
JOB DESCRIPTIONAPPLY JOB DESCRIPTION:
THE PRINCIPAL DESIGN VERIFICATION ENGINEER WILL BE INVOLVED IN DEPLOYING THE LATEST VERIFICATION METHODOLOGIES AND TECHNIQUES FOR THE NEXT GENERATION COMPLEX NETWORKING ASICS. WITH THE HELP OF OTHER VERIFICATION ENGINEERS, HE/SHE WILL BE INVOLVED IN THE SPECIFICATION OF VERIFICATION PLANS, BUILD COMPLEX VERIFICATION ENVIRONMENTS, ANALYSIS OF CIRCUIT AND LOGIC VERIFICATION TOOLS AND METHODS, AS WELL AS THE TRANSITION TO POST-SILICON TEST ENVIRONMENTS.
JOB RESPONSIBILITIES SUMMARY
* Having broad expertise or unique knowledge, uses skills to contribute to development of company objectives and principles and to achieve goals in creative and effective ways.
* Exercises independent judgment in methods, techniques and evaluation criteria for obtaining results.
* Acts independently to determine methods and procedures on new or special assignments, may supervise the activities of others
* Specification and implementation of verification methodology that includes developing Test-bench, BFMs, traffic generators, interface protocol checkers and silicon production support flow
* Participates in architecture & RTL design reviews and outlining the overall verification strategy
* Develops direct, random and application level tests to assure full feature coverage
* Develops functional coverage-driven verification using System Verilog assertions
* Mentors verification engineers located in US and India
IDEAL CANDIDATE WILL HAVE A MINIMUM BS+ 12 YEARS OR MS+ 9 YEARS OF RELEVANT VERIFICATION EXPERIENCE, COUPLED WITH STRONG UNDERSTANDING OF LOGIC DESIGN, DESIGN CYCLE, VERIFICATION TOOLS AND METHODOLOGIES AS WELL AS STRONG DESIGN DEBUG SKILLS. OTHER CHARACTERISTICS INCLUDE:
* Hands-on experience in using advanced verification tools and methodologies like UVM/OVM
* Verification experiences in high-speed serial interconnect protocols like Interlaken, XAUI, PCIe
* Proficient in Verilog and System Verilog concepts
* Knowledge in Ethernet Protocol and Networking system level concepts
* Hands-on experience or familiarity in one or more of the following areas:
* Hardware/Software co-simulation using C-models and System Verilog
* Gate simulations and Formal verification
* Functional coverage and code-coverage techniques and analysis
* Regression setup scripts (in shell, Tcl/Tk, Perl, etc.)
* Familiarity with simulators like VCS, MTI and debug tools like Debussy is must
* Must be highly motivated and skillful at solving difficult technical problems
* Must have excellent communication skills to work with geographically dispersed teams
* Typically requires a minimum of 12+ years of relevant experience. At this level, post-graduate coursework may be expected
IF YOU ARE LOCATED OUTSIDE USA, PLEASE BE SURE TO FILL OUT A HOME ADDRESS AS THIS WILL BE USED FOR FUTURE CORRESPONDENCE.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability or protected veteran status.