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Lead Low Latency Architect / Engineer

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POST DATE 8/9/2016
END DATE 12/19/2016

Investment Bank New York, NY

New York, NY
AJE Ref #
Job Classification
Full Time
Job Type
Company Ref #


The role is for an FTE New Hire in New York providing engineering/architecture leadership for high performance, low latency electronic trading network infrastructure.

The candidate would interact with the business in an engineering capacity and liase with counterparts in computing, security and various external parties like exchanges, clients to come up with an optimal network design.

This is a ED level role. Electronic trading programs require an intimate working knowledge of low latency network design, precision timing, exchange/colo connectivity, multicast routing and market data distribution, dynamic routing (OSPF & BGP), NAT, QoS, Matrix switching, 29West and network instrumentation like Corvil, exchange protocols, application troubleshooting, TCP/IP optimizations, load balancing with A10. Any FPGA knowledge is a plus.

The role requires the candidate to provide Level 4 Engineering support for major operational incidents as well as providing SME guidance for peers. The role holder is also expected to provide thought leadership on emerging technologies and architectures.

CCIE and intimate hands on knowledge of low latency network designs, NTP, precision timing protocol,exchange connectivity, multicast routing and market data distribution, dynamic routing (OSPF & BGP), QoS, 29 West, Matrix switching and network instrumentation- taps., SPAN, netflow, sFlow, Corvil etc,

Understand timing well, GPS/PPS, PTP, NTP, Timekeeper(different stratum levels)

Strong knowledge of Cisco and Arista LL switch architecture (3064s, 3548s, 3132s, 5696, 7150s)

Understand financial applications / protocols

Know concept of what an OR , SORT, client Gateway, POOL, feed handler, and matching engine servers

Familiar with standard FIX protocol, in addition to other proprietary order flow protocols

Understand raw MD flows/and associated exchanges (understand sequencing of MD flows and gap

If familiar with LBM/29west, and IB protocol a plus

Understand concept of Kernel Bypass (using Solarflare NICs)

Understand what it takes to instrument a LL environment (experience with tools, Corvils, Cpacket,

Tradeview, Probes, aggregation switches, etc)

NAT, MPLS, IPSec, A10 load-balancer, Arista, Cisco, Corvil, FSM Labs and Spectracom low latency products. Familiarity with merchant/vendor silicon low latency product. Virtualization, MPLS and security best practices. 40G/100G ethernet and microwave networks. FPGA knowledge is a plus.