Physical Design Engineer
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POST DATE 8/19/2016
END DATE 12/19/2016
Santa Clara, CA
* Team is responsible for delivering physical implementations of high speed custom processors for server and mobile applications
* This position is for floorplanning/place and route, power grid and clock tree design and analysis; core level timing; signal integrity closure; extraction; DRC and LVS
* The engineer will need to use semi-custom layout where appropriate to maximize density, performance, and power efficiency. Implement DFM and DFT requirements.
* 10+ years experience in physical design
* Power Grid Design
* Place and Route
* Static Timing Analysis
* Physical Verification Cadence/Synopsys/Mentor
* EDA CAD tool experience Advanced technology experience o10nm, 14/16nm oFinFet
* The candidate should be able to work with a team of engineers on all aspects of Physical Design tasks on ASIC solutions in next generation technologies
* Responsibilities include: Floor Planning, Clock Tree Design, Place and Route, PDN, Timing analysis and closure
* Perform various physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield) at the chip and block levels
* Manage schedules and support cross-functional engineering effort to drive to signoff closure for tapeout