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POST DATE 8/26/2016
END DATE 10/20/2016
JOB DESCRIPTIONJOB DESCRIPTION:
This position is responsible for, but not limited to, the following job duties:
* Work as part of a physical design team implementing chips from netlist to GDSii.
* Responsible for chip floorplaning, design partition and block pin assignment on multi-millions gates design.
* Perform blocks automatic place and route (APR), timing closure, physical verification, IR/EM (electro-migration) analysis.
* Work on chip assembly and timing verification.
* Work on script development to make physical design flow more efficient.
IF YOU ARE LOCATED OUTSIDE USA, PLEASE BE SURE TO FILL OUT A HOME ADDRESS AS THIS WILL BE USED FOR FUTURE CORRESPONDENCE.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability or protected veteran status.