Principal Hardware Engineer
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POST DATE 9/10/2016
END DATE 11/17/2016
ARRIS Group, Inc.
E6000 hardware engineering performing FPGA and Digital Signal Processing design. Engineer will be part of a team implementing direct digital synthesis and digital modulation of packet oriented data to/from RF transmission mediums. Experienced in implementing digital signal processing algorithms in FPGA's. FPGA designs are modeled in Matlab and implemented in an HDL language. Job includes architectural exploration with Matlab and/or C , device design, design verification, building the simulation environment and creating and maintaining test benches. Candidate must also possess strong circuit design knowledge and be comfortable with RF circuitry.
Key Duties & Responsibilities
Be experienced in designing with Digital Signal Processing (DSP) techniques such as Discrete and Fast Fourier Transforms (DFT/FFT), Inverse Fourier Transforms (IFT), Finite Impulse Response Filters (FIR), Infinite Impulse Response Filters(IIR).
Be familiar with Quadrature signals. Experience with modulators and direct digital synthesis a plus.
Have experience trading off DSP algorithms implementation approaches against FPGA circuit architectures.
Architect and design medium to large FPGAs using an HDL language from high level requirements.
Perform algorithm development and simulation with Matlab tools.
Perform FPGA verification using Modelsim MTI or similar simulation tool suite. Verification tests must be written in an HDL, C and/or Matlab and run in a self-checking mode including creating models for providing stimulus and checking system outputs.
FPGA synthesis and layout using Synplicity or Altera/Xilinx synthesis tools tool suites.
Work with RF design team and trade off digital and analog design techniques for optimum designs.
Develop and manage verification plans including functional operation, SI verification, timing verification, stress testing, standards compliance, EMC/EMI compliance, system test.
Develop design documentation including, design description, test results, factory test requirements, hardware/software interface, etc.
Maintain all design files and supporting files in a source management system.
Verify and debug designs in a laboratory environment using spectrum and/or logic analyzers and other test equipment.
Assist software development via in-system debugging.
Document, debug and fix any problems found.
Follow established ISO9000 process and documentation requirements.
Participate in design reviews.
You must have one of the following degrees: BSEET/BSEE/BSCS along with 6-9 years of technical experience with at least 2 years of DSP design and at least 1 year of ASIC/FPGA design or simulation.
-Experience with DSP filter design including DFT, FFT, FIR or IIR design.
-Be comfortable with communicating in the mathematical lingo of digital signal processing.
-Must have VHDL, Verilog or System Verilog programming and simulation experience and have been responsible for the design or verification of a medium to large CPLD, ASIC or FPGA device or a major sub-block within.
-Expert knowledge of general digital circuitry and microprocessors.
-comfortable using standard lab instruments, meters, oscilloscopes, spectrum analyzers, etc.
-Proficient using Windows and/or Unix/Linux computing environments.
-Working knowledge of MS Excel and Word.
Experience (type & duration): Greater than 10 years experience, greater than 4 years designing DSP algorithms and 2 or more years modeling and simulating ASICs/FPGAs.
-Experienced Matlab or Labview user.
-Experience with FFT, IFT, FIR, and IIR filter design
-Familiarity with software defined radio and/or modulator design.
-Experience with Synplicity synthesis, Altera or Xilinx tool sets.
-Experience working closely with RF circuit designs.
-Scripting skills with perl , python, tcl, shell or equivalent tools.
-Ability to work independently.
-Experience with high speed data path and memory interfaces
-Design of ATM or IP packet processing systems.
-Besides VHDL or Verilog, experience with SystemVerilog, SystemC, Vera or the e language. UVM (Universal Verification Methodology) experience a plus.
-Signal integrity design or simulation experience
-Telecommunications systems operation or maintenance experience.
-Software design experience with C or C
-MS Excel and Word proficiency.
-Strong verbal communicator
-Comfortable using writing and documentation skills.
Relo not provided for this position.
As an EOE/AA employer, ARRIS will not discriminate in its employment practices due to an applicants race, color, religion, sex, national origin, and veteran or disability status.