R&D Engineer IC Design 4
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POST DATE 9/2/2016
END DATE 11/15/2016
Santa Clara, CA
JOB DESCRIPTIONJOB DESCRIPTION:
Do DFT insertion and physical design of SoCs at the full-chip level and module level. Analyse and validate timing specifications, provide design feedback to logic designers to ensure timing closure and high DFT coverage. Do timing and power analysis, determine fixes for violations or quality improvements, and implement fixes. Demonstrate high level of competency in all aspects of place-and-route, static timing analysis and timing closure.
IF YOU ARE LOCATED OUTSIDE USA, PLEASE BE SURE TO FILL OUT A HOME ADDRESS AS THIS WILL BE USED FOR FUTURE CORRESPONDENCE.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability or protected veteran status.