Staff Design Verification Engineer
Xilinx, Inc - San Jose, CA
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Xilinx, Inc. (NASDAQ: XLNX) is the world s leading provider of All Programmable technologies and devices, going beyond traditional programmable logic to enable both hardware and software programmability, integrate both digital and analog mixed-signal functions, and allow new levels of programmable interconnect in both monolithic and multi-die 3D ICs. The company s products are coupled with a next-generation design environment and IP to service a broad range of customer needs, from programmable logic to programmable systems integration.
Xilinx chips are designed into automotive infotainment and driver safety, ultrasound imaging, robotically-assisted surgical systems, IT gear for wireless computing and mobile applications, consumer 3-D TVs, mobile communications used on the networked battlefield and even sophisticated space vehicles exploring the outer reaches of the universe.
Xilinx FDST Verification group is looking for a Senior Verification Engineer to verify high speed SerDes design.
The individual will help design, develop and use simulation and verification environments, at block and full chip FPGA level, to prove the functional correctness of SerDes designs. The ideal candidate is one who has a proven track record on driving successful verification execution on high performance IP and/or VLSI designs.
Require BS w/ 6+ yrs or MS w/ 4+ yrs or PhD w/ 2+ yrs in Electrical Engineering, Computer Engineering or Computer Science.
Candidate is expected to be a strong team player with good communication skills.
Require experience with development of OVM, UVM, VMM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments.
Require strong understanding of state of the art of verification techniques, including assertion and metric-driven verification.
Require familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management.
Strong understanding of different phases of ASIC and/or full custom chip development is required.
Experience in establishing verification methodology, tools and infrastructure for high performance IP and/or VLSI designs is a plus.
Experience with mixed-signal verification tools and methodology is a plus.
Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan) is a plus.
Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.
- Applicants are treated throughout the employment process without regard to race, color, religion, national origin, citizenship, age, sex, marital status, ancestry, physical or mental disability, veteran status or sexual orientation. The information requested here is not gathered for employment decisions. It is used only for compliance with Federal laws. Your responses are strictly voluntary, and any information provided will remain confidential. If you choose not to "self-identify", you will not be subject to any adverse treatment. -