Senior Level Functional Verification Engineer

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POST DATE 8/16/2016
END DATE 12/19/2016

Confidential Company San Jose, CA

Location
San Jose, CA
AJE Ref #
575898785
Job Classification
Full Time
Job Type
Regular
Company Ref #
28794989

JOB DESCRIPTION

The client is looking below qualities from the candidate and if you think you are matching with the qualities please feel free to contact me. Thanks!

RESPONSIBILITIES:

* The verification engineer will be responsible for developing and maintaining test bench components and behavioral models of analog blocks
* He/she will also own selected test scenarios and regressions

MINIMUM QUALIFICATIONS:

* The candidate must have at least 5 years of experience with real number models and functional verification of mixed signal chips, as well as an MSEE

PREFERRED QUALIFICATIONS:

* It would be very helpful if the candidate was proficient in SystemVerilog and had a few years of experience with UVM

EDUCATION:

* Master of Science in Electrical Engineering (MSEE)