Senior Level Functional Verification Engineer 8/16/2016
San Jose, CA
JOB DESCRIPTIONAPPLY The client is looking below qualities from the candidate and if you think you are matching with the qualities please feel free to contact me. Thanks!
* The verification engineer will be responsible for developing and maintaining test bench components and behavioral models of analog blocks
* He/she will also own selected test scenarios and regressions
* The candidate must have at least 5 years of experience with real number models and functional verification of mixed signal chips, as well as an MSEE
* It would be very helpful if the candidate was proficient in SystemVerilog and had a few years of experience with UVM
* Master of Science in Electrical Engineering (MSEE)