This company is committed to hiring Veterans

Senior Staff Verification Engineer

This job is no longer active. View similar jobs.

POST DATE 8/23/2016
END DATE 11/19/2016

Xilinx, Inc San Jose, CA

Company
Xilinx, Inc
Job Classification
Full Time
Company Ref #
150885
AJE Ref #
575958021
Location
San Jose, CA
Experience
Entry Level (0 - 2 years)
Job Type
Regular
Education
Bachelors Degree

JOB DESCRIPTION

APPLY
United States-California-San Jose
Job: Design Engineering
Primary Location: Full-time
Description: Xilinx is the world's leading provider of All Programmable FPGAs, SoCs and 3D ICs. These industry-leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. Our All Programmable devices underpin today's most advanced electronics. Among the broad range of end markets we serve are:

* Aerospace/Defense

* Automotive

* Broadcast

* Consumer

* High Performance Computing

* Industrial / Scientific / Medical (ISM)

* Wired

* Wireless



Xilinx FDST Verification group is looking for a Senior Staff Verification Engineer to verify high speed SerDes design.



The individual will help design, develop and use simulation and verification environments, at block and full chip FPGA level, to prove the functional correctness of SerDes designs.

The ideal candidate is one who has a proven track record on driving strategies and successful verification execution on high performance IP and/or VLSI designs.

Organization:



* Require BS w/ 9 yrs or MS w/ 7 yrs or PhD w/ 5 yrs in Electrical Engineering, Computer Engineering or Computer Science.

* Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the FPGA design teams with an eye towards improving overall product quality.

* Require experience with development of OVM, UVM, VMM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test full chip FPGA fabric and SOCs.

* Require strong understanding of state of the art of verification techniques, including assertion and metric-driven verification.

* Require familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management.

* Strong understanding of different phases of ASIC and/or full custom chip development is required.

* Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus.

* Experience with DSP and communication systems is a plus.

* Verification Experience in DDR4, SERDES, PCIe, CMAC/ILKN, Video Encoders, Processors, Graphics is a plus

* Experience with mixed-signal verification tools (e.g. VCS/XA) and methodology is a plus.

* Experience with FPGA programming and software is a plus.

* Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan) is a plus.

* Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.


Schedule: Nov 3, 2016, 5:43:29 PM
Job Posting: Xilinx is an equal opportunity and affirmative action employer. Applicants and employees are treated throughout the employment process without regard to race, color, religion, national origin, citizenship, age, sex, marital status, ancestry, physical or mental disability, veteran status, gender Identity or sexual orientation. The self-identification information requested is not gathered for employment decisions. It is used only for compliance with US Federal laws. Your responses are strictly voluntary, and any information provided will remain confidential. If you choose not to "self-identify", you will not be subject to any adverse treatment.
Unposting Date: false

Xilinx is an equal opportunity and affirmative action employer. Applicants and employees are treated throughout the employment process without regard to race, color, religion, national origin, citizenship, age, sex, marital status, ancestry, physical or mental disability, veteran status or sexual orientation. The information requested here is not gathered for employment decisions. It is used only for compliance with US Federal laws. Your responses are strictly voluntary, and any information provided will remain confidential. If you choose not to "self-identify", you will not be subject to any adverse treatment