Signal/Power Integrity Engineer

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POST DATE 8/10/2016
END DATE 10/25/2016

Broadcom Limited Santa Clara, CA

Company
Broadcom Limited
Job Classification
Full Time
Company Ref #
R001006-Santa Clara
AJE Ref #
575839360
Location
Santa Clara, CA
Experience
Entry Level (0 - 2 years)
Job Type
Regular
Education
Bachelors Degree

JOB DESCRIPTION

APPLY
JOB DESCRIPTION:

An experienced signal integrity engineer is being sought for analysis and validation of high speed DRAM interfaces and power distribution network. The successful candidate will be part of signal/power integrity/simulation team and will participate in the definition of chip, package and printed circuit board (PCB). Within a concurrent engineering environment, the individual will be part of a larger team with system architects, ASIC engineers, and other SI/PI engineers in creation of next generation broadband products. The candidate is ideally an expert in DDR DRAM technology and interface signaling with demonstrated experience in these areas.

ESSENTIAL DUTIES AND RESPONSIBILITIES INCLUDE:

* Perform SI/PI and timing analysis in designing working solutions ranging from chip to chip, board to board and system to system.

* Develop channel simulation models and correlate to test structures.

* Perform PCB timing analysis, work with board engineers and layout designers to implement all SI/PI rules, develop layout/SI/PI/PDN checklists.

* Perform SI DVT measurements on boards and correlate simulations with DVT measurements.

* Generating the routing requirements and electrical margins for specific interfaces and verifying their correctness

* Simulating and/or analyzing and/or generating power delivery network requirements

* Develop/simulate models with electromagnetic field solvers: Ansys HFSS and Ansys SIWave

* Ensure the accuracy of models used for simulation.

* Develop test plans to validate signal integrity.

* Understand and analyze concepts such as: insertion loss, return loss, cross talk, eye diagrams

* Review and/or oversee package/pcb layout.

* Optimize PCB Decoupling capacitors (values, quantity and location) based on PDN (Power Distribution Network) impedance profile analysis.

JOB REQUIREMENTS

Required

* Capable of presenting new work/concepts/analysis to SI/PI team.

* Provide technical assessment of projects to SI/PI management team.

* Proficient with Ansys HFSS/SIwave/DesignerSI, HSPICE, & Agilent ADS.

* Proficient with Cadence APD/Allegro

* Expertise with DDR3, DDR4, LPDDR3/LPDDR4 DRAM technologies

* Proficient with lab equipment such as oscilloscopes.

* Strong written and oral communication skills

* The candidate for this position must be able to work independently, have the ability to put in place new procedures, and complete multiple parallel tasks on time.

* Must have ability to read and interpret schematics and PCB layout.

* Good team player able to work with other SI/PI engineers and managers across geography in a matrix organization.

* Previous exposure to SI, chip verification/validation is critical

* Requires a 7 years B.S. in Electrical/Computer Engineering or a related discipline prior experience in chip industry related experience preferred.

* Experience with ASIC lab bring up and design validation on products, a plus

Desired

* Modern script languages : Perl, Python knowledge is desired

IF YOU ARE LOCATED OUTSIDE USA, PLEASE BE SURE TO FILL OUT A HOME ADDRESS AS THIS WILL BE USED FOR FUTURE CORRESPONDENCE.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability or protected veteran status.