System Design Engineer*

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- Candidate will be responsible for designing and verifying infrastructure IP cores, system building blocks, and debug/analysis IP products used in a wide range of systems and on chip networks. Candidate will use creativity and advanced methodologies working with IP and system architects to develop and verify IP to be high quality, high performance, and easy to use. Position involves exposure to the latest generation IP, tools, and FPGA products. The position also offers the opportunity for growth in the area of HDL functional verification using System Verilog and OVM.
- Job Requirements:-Working knowledge and experience in Verilog logic design and simulation-Interest in learning advanced verification methodologies using System Verilog and OVM -Working knowledge of Linux environment and some scripting language such as Perl, PHP, TCL, etc-Strong Oral and Written Communication skills-BSEE/MSEE with 0-5 years of experience Desired:-Experience working with FPGAs or Xilinx products-Experience with standard IP interface protocols such as AMBA AXI
- Applicants are treated throughout the employment process without regard to race, color, religion, national origin, citizenship, age, sex, marital status, ancestry, physical or mental disability, veteran status or sexual orientation. The information requested here is not gathered for employment decisions. It is used only for compliance with Federal laws. Your responses are strictly voluntary, and any information provided will remain confidential. If you choose not to "self-identify", you will not be subject to any adverse treatment.
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