ASIC Physical Design Engr, Sr II 9/19/2017
JOB DESCRIPTIONAPPLY Job Description and Requirements
Job Description & Requirements
*Job Description and Requirements
Synopsys Mixed-Signal IP organization is seeking a highly motivated individual responsible for the physical implementation of complex Mixed signal IPs and testchips across multiple process technologies.
In this role, you will be responsible for the Physical implementation of high speed interface IPs and test-chips, driving all aspects from RTL to GDS including timing and physical sign-off, in close interaction and collaborative team work with multiple functional groups (front end, analog, CAD) and the product team.
The successful candidate:
* Has 7+ years of Physical Design experience with recent contribution to project tape-outs.
* Has intimate knowledge of the full design cycle from RTL to GDSII, including chip level.
* Has solid engineering understanding of the underlying concepts of IC design, implementation flows and methodologies for deep submicron design.
* Has good communication skills, ability to think and communicate at different levels of abstraction, with peer groups as well as customers.
* Has good software and scripting skills (Perl, Tcl, Python); knowledge of CAD automation methods.
* Has a good understanding of industry standards in deep sub-micron designs.
* Autonomous, timely decision maker and able to cope with interrupts.
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