Principal ASIC Design Engineer (AMRD2026) 10/12/2017
JOB DESCRIPTIONAPPLY Organization Overview
Fortinet (NASDAQ: FTNT) protects the most valuable assets of some of the largest enterprise, service provider and government organizations across the globe. The company's fast, secure and global cyber security solutions provide broad, high-performance protection against dynamic security threats while simplifying the IT infrastructure. They are strengthened by the industry's highest level of threat research, intelligence and analytics. Unlike pure-play network security providers, Fortinet can solve organizations' most important security challenges, whether in networked, application or mobile environments - be it virtualized/cloud or physical. More than 310,000 customers worldwide, including some of the largest and most complex organizations, trust Fortinet to protect their brands. Learn more at http://www.fortinet.com, the Fortinet Blog http://blog.fortinet.com/ or FortiGuard Labs http://www.fortiguard.com/.
United States [US]
Principal ASIC Design Engineer (AMRD2026)
Full Time Regular
As a key member of Fortinet's ASIC design team you will help design and architect Fortinet's Next-Generation System-on-Chip FortiASIC to accelerate world's most powerful networking security system. Fortinet's SOC ASIC enables FortiGate to achieve best-in-class throughput with consolidated security and networking capabilities. FortiGate enables distributed enterprises, branch offices and SMBs to leverage the superior protection of Fortinet's Security Fabric. Current generation SOC FortiASIC delivers more than doubled security networking performance over enterprise-class CPUs found in other competing solutions. Next-Generation SOC FortiASIC will further surpass performance of current generation and continue demonstrating Fortinet's leadership with unparalleled data processing power and integrated security features. You will play a principal role in developing next-gen SOC architecture, perform IP integration, chip level RTL design & verification and lead low power design methodology. Candidate must be able to work with self motivation and deliver on commitments with challenging schedules, lead design teams through various phases of ASIC design process including RTL design, chip level verification, coverage analysis, synthesis and STA. Candidate must possess solid knowledge in SOC design techniques, analog IPs, high speed IO protocols, CPF/UPF power design flow and lint/CDC tools. * Work with architecture team to shape micro-architecture of next-generation SOC FortiASIC. * Work with IP teams to review verification test plan, coverage analysis and full-chip simulation. * Design implementation using Verilog HDL and synthesis. * Work with physical design teams to verify constraints, optimize place & route and achieve timing closure. * A self-starter with ability to manage time effectively and work within a diverse team environment.
Requirements * Experienced in design and implementation of complex multi-million gate SOCs.
* Familiarity with high speed IP protocols including SATA, eMMC, USB, PCIe and DDR. * Strong experience designing digital circuits using Verilog HDL. * Strong experience in formal verification of digital design. * Fluent in C, C++, assembly and scripting languages. * Excellent communication skills. Educational Requirement MS & BS in Electrical Engineering or related field with 7+ years of SOC ASIC design experience.
EEOC / AAP
Accommodation: If you are an individual with a disability and require a reasonable accommodation to complete any part of the application process, or are limited in the ability or unable to access or use this online application process and need an alternative method for applying, you may contact Fortinet, Inc at (408) 235-7700 of firstname.lastname@example.org for assistance.
EEO: All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.