R&D Engineer, Sr II 9/17/2017
JOB DESCRIPTIONAPPLY Synopsys Inc. is looking for multiple software engineers to work on the industry's fastest emulation system, Zebu Server, which offers the industry's largest design capacity, supporting SOC chips as large as 3 billion gates based on high-density 28 nano-meter FPGA technology. In Zebu emulation flow, the design under test is partitioned into multiple parts, each of which is compiled into a low level binary bit-stream that can be downloaded and run on an underlying FPGA in the emulation hardware. Individuals that fill these positions will work in a global multi-site team specializing in areas such as logic partitioning, placement and routing, static timing analysis, and timing performance optimization to design and develop the next generation emulation backend technologies used in Zebu software tools. The responsibilities include active involvement in the entire software development process for the new Zebu backend tools, covering specification, design, implementation, benchmarking, and validation. It is also required to share the responsibility of supporting the existing Zebu backend software tools in production.
* MS/Ph.D. in Computer Science, Computer Engineering, or Electrical Engineering.
* Multiple years of industrial experience in EDA software development, especially in partitioning, floorplanning, place-and-route, static timing analysis, or timing closure for large capacity and high performance designs.
* Demonstrated experience with efficient algorithm and data structure design.
* Understanding of digital logic design, FPGA architecture, and hardware description language is preferred.
* Highly developed interpersonal skills and the ability to work well either in a team-based environment or independently.
* Experience in use of a logic simulation tool (such as VCS, etc) is a plus.