Digital Design Engineer, Senior Principal 7/8/2019
JOB DESCRIPTIONAPPLY DESCRIPTION
Digital Design Engineer, Senior Principal
The engineer will be responsible for design and verification of Forward Error Correction decoders for next generation optical networking chips. Responsibilities include RTL design/coding, verification, synthesis and static timing analysis of next generation optical networking ASICs. Typical activities include RTL coding, writing verification plans and execution, synthesis, formal verification (LEC), static timing analysis, and circuit level analysis.
Required Skills & Experience
A Master s in Engineering with 5+ years relevant experience, or a Ph.D. is required.The successful candidate will be highly experienced with the IC/ASIC design/verification flow with proven track record of designing FEC decoders for high speed communication systems like Reed Solomon, BCH, Turbo codes or ldpc. Experience in CMOS power analysis and modeling desirable. Good working knowledge of designing, modeling and model verification. High speed digital communications knowledge highly desirable. Fluency with Verilog, System Verilog or VHDL. Strong knowledge in C , C++ or Matlab is compulsory. Experience in RTL debugging using conventional EDA tools like Cadence IES, Mentor Graphics Modelsim or Synopsys VCSGood knowledge of scripting in Python, tcl, or Perl.Experience with low power design and verification flows highly desirable. Hands-on experience with synthesis, formal verification, static timing analysis, highly desirable
Inphi is an Equal Opportunity and Affirmative Action Employer. Inphi provides equal employment opportunities to all qualified applicants and employees without regard to race, sex, sexual orientation, gender identity, national origin, color, age, religion, protected veteran or disability status, genetic information, or any other basis protected under applicable federal, state or local laws.