Digital Design Engineer - Staff
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POST DATE 7/8/2019
END DATE 9/21/2019
Digital Design Engineer, Staff
The engineer will be responsible for design and verification of embedded microprocessor subsystem. He/She will be involved in logic design and verification of AMBA based AXI/AHB and related bus system, various slow speed peripherals logic like uart, i2c, spi, mdio etc. Responsibilities include RTL design/coding, verification, synthesis and static timing analysis of next generation optical networking ASICs. Typical activities include RTL coding, writing verification plans and execution, synthesis, formal verification (LEC), static timing analysis, and circuit level analysis.
Required Skills & Experience
A Master s in Engineering with 3+ years relevant experience is required.
The successful candidate will be experienced with the IC/ASIC design/verification flow. Good working knowledge of designing embedded microprocessor subsystem for communication Asics. High speed digital communications knowledge highly desirable.Fluency with Verilog, System Verilog or VHDL. Experience in RTL debugging using conventional EDA tools like Cadence IES, Mentor Graphics Modelsim or Synopsys VCSGood knowledge of scripting in Python, tcl, or Perl.Experience with low power design and verification flows highly desirable. Hands-on experience with synthesis, formal verification, static timing analysis, highly desirable.
Inphi is an Equal Opportunity and Affirmative Action Employer. Inphi provides equal employment opportunities to all qualified applicants and employees without regard to race, sex, sexual orientation, gender identity, national origin, color, age, religion, protected veteran or disability status, genetic information, or any other basis protected under applicable federal, state or local laws.